Precise failure localization using automated layout analysis of diagnosis candidates
Proceedings of the 45th annual Design Automation Conference
Physically-aware N-detect test pattern selection
Proceedings of the conference on Design, automation and test in Europe
Automated failure population creation for validating integrated circuit diagnosis methods
Proceedings of the 46th Annual Design Automation Conference
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior of arbitrary defects in digital circuits. To justify this claim, this paper describes two types of logic faults (state transition and signal line faults) and formally shows how fault tuples can be used to precisely represent any number of faults of this kind. The capability of fault tuples to capture misbehaviors beyond logic faults is then illustrated using many examples of varying degree of complexity. In particular, the ability of fault tuples to modulate fault controllability and observability is examined. Finally, it is described how fault tuples can and have been used to enhance testing tasks such as fault simulation, test generation, and diagnosis, and enable new capabilities such as interfault collapsing and application-based quality metrics