A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Defect Modeling Using Fault Tuples
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated failure population creation for validating integrated circuit diagnosis methods
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 48th Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Traditional software-based diagnosis of failing chips typically identifies several lines where the failure is believed to reside. However, these lines can span across multiple layers and can be very long in length. This makes physical failure analysis difficult. In contrast, there are emerging diagnosis techniques that identify both the faulty lines as well as the neighboring conditions for which an affected line becomes faulty. In this paper, an approach is presented to improve failure localization by automatically analyzing the information associated with the outcome of diagnosis. Experimental results show a significant improvement in failure localization when this method is applied to 106 real IC failures.