Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis
Journal of Electronic Testing: Theory and Applications
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Yield Analysis of Logic Circuits
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
Precise failure localization using automated layout analysis of diagnosis candidates
Proceedings of the 45th annual Design Automation Conference
Physically-aware N-detect test pattern selection
Proceedings of the conference on Design, automation and test in Europe
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
IEICE - Transactions on Information and Systems
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
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A technique for performing logic diagnosis of defects that cause interconnects in a digital logic circuit to become open or highly resistive is presented. The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect on an interconnect and diagnosis algorithms that leverage the diagnostic model. The technique circumvents the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitances, and is easily integratable into conventional test and simulation tools. Other aspects of the technique include a path-tracing procedure to limit the number of interconnects that need to be analyzed and extensions for multiple defects. Experimental results include simulation results on processor functional blocks and silicon results on a chipset from artificially induced defects and production fallout.