Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Modelling the Unmodellable: Algorithmic Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
On Improving the Accuracy Of Multiple Defect Diagnosis
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Bridge fault diagnosis using stuck-at fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in which a fault manifests itself as a non-logical voltage level at the fault site. Previously, explicit enumeration was suggested to deal with such a problem. However, it is often too time-consuming because the CPU time is exponentially proportional to fanout degree of the circuit under diagnosis. To speed up this process, we present an implicit enumeration technique using symbolic simulation. Experimental results show that the CPU time can be improved by several orders of magnitude for the ISCAS85 benchmark circuits while locating the faults accurately.