Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Locating functional errors in logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Functional approaches to generating orderings for efficient symbolic representations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Towards the logic defect diagnosis for partial-scan designs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis
Journal of Electronic Testing: Theory and Applications
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Connection Errors Location and Correction in Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On Efficient Error Diagnosis of Digital Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Checkpointing and Its Applications
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Error Diagnosis of Sequential Circuits Using Region-Based Model
Journal of Electronic Testing: Theory and Applications
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
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