VERIFY: a program for proving correctness of digital hardware designs
Artificial Intelligence - Special volume on qualitative reasoning about physical systems
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A logic verifier based on Boolean comparison
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An ALGOL-like computer design language
Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Locating logic design errors via test generation and don't-care propagation
EURO-DAC '92 Proceedings of the conference on European design automation
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On diagnosis and correction of design errors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Connection Errors Location and Correction in Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Efficient Error Diagnosis of Digital Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistencies that may exist between the functional-level description and its gate-level implementation. In this paper we present a method that determines the areas, within the gate-level circuit, that contain the functional errors. The indicated areas are shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.