Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Locating functional errors in logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Locating logic design errors via test generation and don't-care propagation
EURO-DAC '92 Proceedings of the conference on European design automation
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On error correction in macro-based circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Logic rectification and synthesis for engineering change
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A method for automatic design error location and correction in combinational logic circuits
Journal of Electronic Testing: Theory and Applications
The use of random simulation in formal verification
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper addresses the problem of locating errorsources in an erroneous combinational circuit. We use afault simulation-based technique to approximate eachsignal's correcting power. The correcting power of aparticular signal is measured in terms of the signal'scorrectable ser, namely, the maximum set of erroneousinput vectors that can be corrected by re-synthesizing thesignal. Only the signals that can correct every erroneousinput vector are considered as a potential error source. Ouralgorithm offers three major advantages over existingmethods. First, unlike symbolic approaches, it is applicablefor large circuits. Secondly, it delivers more accurateresults than other simulation-based approaches because itis based on a more stringent condition for identifyingpotential error sources. Thirdly, it can be easily generalizedto identify multiple errors. Experimental results ondiagnosing circuits with one and two random errors arepresented to show the effectiveness and efficiency of thisnew approach.