Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Locating functional errors in logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Locating logic design errors via test generation and don't-care propagation
EURO-DAC '92 Proceedings of the conference on European design automation
On error correction in macro-based circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A method for automatic design error location and correction in combinational logic circuits
Journal of Electronic Testing: Theory and Applications
Pattern matching algorithms
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Logic design error diagnosis and correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
From Error to Error: Logic Debugging in the Many-Core Era
Electronic Notes in Theoretical Computer Science (ENTCS)
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process or due to specification changes. We incrementally use simulation to identify suspect nets, and then attempt correction based on our error model. We use multiple iterations to handle multiple errors. Experimental results on ISCAS'85 benchmarks are shown for circuits containing up to four random errors. Diagnosis and correction can be done quickly, with the bulk of the time going to diagnosis. Our tool is accurate in that even with multiple errors present, the corrected circuit is identical to the original most of the time.