Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Diagnosis and correction of multiple logic design errors in digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic Design Validation via Simulation and Automatic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Elements of the Theory of Computation
Elements of the Theory of Computation
Collection and Analysis of Microprocessor Design Errors
IEEE Design & Test
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On efficient error diagnosis of digital circuits
Proceedings of the IEEE International Test Conference 2001
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Incremental Diagnosis of Multiple Open-Interconnects
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Incremental Diagnosis and Correction of Multiple Faults and Errors
Proceedings of the conference on Design, automation and test in Europe
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ErrorTracer: design error diagnosis based on fault simulation techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In today's complex and challenging VLSI design process, multiple logic errors may occur due to the human factor and bugs in CAD tools. The designer often faces the challenge of correcting an erroneous design implementation. This study describes a simulation-based logic debugging solution for combinational circuits corrupted with multiple design errors. Unlike other simulation-based techniques that identify all errors at once, the proposed method works incrementally. At each iteration of incremental debugging, a single candidate location is rectified with linear time algorithms. This is done so that the functionality of the erroneous design gradually matches the correct one. A number of theorems, heuristics and data structures help identify a single candidate solution at each iteration and they also guide the search in the large solution space. Experiments on benchmark circuits confirm the effectiveness of incremental logic debugging.