Locating functional errors in logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Exploiting hierarchy for multiple error correction in combinational circuits (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
Error Diagnosis in Equivalence Checking of High Performance Microprocessors
Electronic Notes in Theoretical Computer Science (ENTCS)
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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