Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
A method for automatic design error location and correction in combinational logic circuits
Journal of Electronic Testing: Theory and Applications
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On diagnosis and correction of design errors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Connection Errors Location and Correction in Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
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Equivalence checking of two circuits is performed at several stages in the design cycle of hardware designs and various commercial equivalence checkers, mostly based on Boolean logic, are already in the market. Design Error Diagnosis and Correction (DEDC) methods come into play when equivalence checking has proven two circuits different. In many cases, DEDC methods can locate and correct design errors fully automatically.In this paper, we present an efficient symbolic method for automatic error correction of both combinational and synchronous sequential circuits. We first address the problem of rectifying combinational circuits and then show how the problem of rectifying sequential circuits can be reduced to a combinational problem without unrolling the combinational logic parts.In addition, we introduce several optimizations to our algorithm. All optimizations are safe, meaning that they neither affect the number of computed solutions nor do they decrease the quality of results. Our experimental results show that the discussed optimization strategies can make the rectification procedure 2 to 16 times faster than the un-optimized algorithm.