Locating functional errors in logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
System design methodology of ultraSPARC-I
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A method for automatic design error location and correction in combinational logic circuits
Journal of Electronic Testing: Theory and Applications
A logic verifier based on Boolean comparison
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
Design error diagnosis in sequential circuits
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Connection Errors Location and Correction in Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Connection Errors Location and Correction in Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On Efficient Error Diagnosis of Digital Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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We present new diagnostic algorithms for localizing connection errors in combinational circuits. Three types of errors are considered: extra, missing, and bad connection errors. Special test patterns are generated to rapidly locate the error. The algorithms are integrated within the Prevail^{TM} system. Results on benchmarks show that the error is always located, within a time proportional to the product of the circuit size, and the number of used patterns.