A logic verifier based on Boolean comparison

Authors:
Gotaro Odawara;Masahiro Tomita;Osamu Okuzawa;Tomomichi Ohta;Zhen-quan Zhuang
Affiliations:
Department of Precision Engineering, Faculty of Engineering, University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo, 113 JAPAN;Department of Precision Engineering, Faculty of Engineering, University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo, 113 JAPAN;Department of Precision Engineering, Faculty of Engineering, University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo, 113 JAPAN;Department of Precision Engineering, Faculty of Engineering, University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo, 113 JAPAN;Department of Electronic Engineering, University of Science and Technology of China, Hefei, Anhui, People's Republic of CHINA
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

Citing 3
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Abstract

This paper proposes a logic VERIFIER, which verifies the correctness of the gate-level design by comparing it with the behavioral description.An improved Boolean comparison technique, which assures the absence of errors without designer's assist, is proposed. The partitioning and the minimization techniques are effective to reduce the storage required, and indispensable to verify practical sized circuits.If the design is judged incorrect, the system analyzes the result and show the area containing errors.Experimental results have proved that the VERIFIER can detect design errors completely, and indicate them to the designers in comprehensible form.