Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A computational logic handbook
A computational logic handbook
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis of Digital Design from Recursive Equations
Synthesis of Digital Design from Recursive Equations
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment
EURO-DAC '90 Proceedings of the conference on European design automation
Formal verification of behavioral VHDL specifications: a case study
EURO-DAC '94 Proceedings of the conference on European design automation
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems
EURO-DAC '94 Proceedings of the conference on European design automation
Towards verifying VHDL descriptions of processors
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A classification of design steps and their verification
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Automatic diagnosis may replace simulation for correcting simple design errors
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A refinement calculus for the synthesis of verified hardware descriptions in VHDL
ACM Transactions on Programming Languages and Systems (TOPLAS)
Quantifying Design Quality Through Design Experiments
IEEE Design & Test
Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITY
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Connection Errors Location and Correction in Combinational Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An integrated environment for HDL verification
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Formalization of a parameterized parallel adder within the coq theorem prover
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluating possibilities for formally sound simulation and verification of VHDL
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
A logic to specify and verify synchronous transitions
IW-FM'99 Proceedings of the 3rd Irish conference on Formal Methods
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Prevail, a formal verification environment for proving the equivalence of two very-high-speed integrated circuit hardware description language (VHDL) design architectures, is described. For simple bit-level combinational descriptions, the environment calls upon a tautology checker. For parameterized repetitive structures and for more abstract sequential designs, the program translates descriptions into recursive functions according to predefined templates and generates a theorem acceptable to the Bover-Moore theorem prover. The specification, implementation, and functional representation of a sequential example are presented.