The verification of a bit-slice ALU
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
An intelligent module generator environment
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
Representation and symbolic manipulation of linearly inductive Boolean functions
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
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In this paper the correctness of parameterised hardware module generators is examined. These modules are the basic building blocks for the CATHEDRAL II silicon compiler and therefore their correctness is vital. The proof of their functional correctness by means of the Boyer-Moore theorem prover will be discussed. It will be shown that later modifications made to the module generators can be proven correct very easily, starting from the proofs of the original module. The specific module generator that will be discussed is a carry-bypass ALU based on the Mead & Conway ALU. A general scheme will be presented to verify layout instances of these modules with respect to their behavioral specification.