Formal verification of behavioral VHDL specifications: a case study
EURO-DAC '94 Proceedings of the conference on European design automation
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment
EURO-DAC '90 Proceedings of the conference on European design automation
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