Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
EURO-DAC '92 Proceedings of the conference on European design automation
Symbolic Model Checking
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
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