A classification of design steps and their verification

VLSI design language standardization effort in Japan

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference

Semantics of a hardware design language for Japanese standardization

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference

The design cube: a new model for VHDL designflow representation

EURO-DAC '92 Proceedings of the conference on European design automation

Verification of VHDL designs using VAL

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference

The VHDL Handbook

The VHDL Handbook

Software Engineering Economics

Software Engineering Economics

Formal Verification of VHDL Descriptions in the Prevail Environment

IEEE Design & Test