Semantics of a hardware design language for Japanese standardization

Authors:
H. Yasuura;N. Ishiura
Affiliations:
Department of Electronics, Faculty of Engineering, Kyoto University, Kyoto 606, Japan;Department of Electronics, Faculty of Engineering, Kyoto University, Kyoto 606, Japan
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

We propose a new approach to define a formal semantics of a hardware design language (HDL) in Japanese LSI design language standardization project. Our approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, we can describe vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. We introduce a new computation model of hardware behaviour called NES (Nondeterministic Event Sequence) model. NES model is a very simple model of the computation in digital systems and provides an intuitive understanding of concurrent behaviour of HDL description without loss of mathematical strictness.