The making of VIVID: a software engineering perspective
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An object oriented approach to CAD tool control within a design framework
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Semantics of a hardware design language for Japanese standardization
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
CEDIF: a data driven EDIF reader
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Fast online/offline netlist compilation of hierarchical schematics
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A data structure for circuit net lists
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Circuit compilers don't have to be slow
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The String-to-String Correction Problem
Journal of the ACM (JACM)
Communications of the ACM
Spelling correction in systems programs
Communications of the ACM
SCALD: Structured Computer-Aided Logic Design
DAC '78 Proceedings of the 15th Design Automation Conference
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Using controlled experiments in layout
ACM SIGDA Newsletter
| Hi-index | 0.00 |
The argument for electronic circuit logic design tool interchangeability by means of source-destination specific net list translation within a framework of Unix operating system commands is presented. After describing the information necessary for design verification using an assortment of diverse tools, various design tool interchangeability alternatives are considered. Discussion of net list translator examples, Unix like design movement programs, and translation speed complete the argument.