The C programming language
Benchmarks for cell-based layout systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Computer algorithms: introduction to design and analysis
Computer algorithms: introduction to design and analysis
Algorithm 447: efficient algorithms for graph manipulation
Communications of the ACM
Graph Algorithms
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
SCALD: Structured Computer-Aided Logic Design
DAC '78 Proceedings of the 15th Design Automation Conference
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
An hierarchical language for the structural description of digital systems
DAC '77 Proceedings of the 14th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A new placement level wirability estimate with measurements
ACM SIGDA Newsletter
CAD tool interchangeability through Net list translation
ACM SIGDA Newsletter
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A data structure for storing and processing electrical circuit net lists is described. The basic data structure is not new, but the version described here is novel in three specific ways. It adds separate structures (arrays) for cell type and I/O pad specific information, stores net lists defined in terms of primitive elements or cells as two superimposed symmetric incidence list form directed graphs, and separates primitive element input and output lists to allow signal flow traversal. This paper concentrates on computer program level implementation details and on various practical problems arising in circuit net list processing. Finally, the structure's construction cost and algorithmic efficiency is discussed.