Constructing test cases for partitioning heuristics
IEEE Transactions on Computers
Some experimental results on placement techniques
25 years of DAC Papers on Twenty-five years of electronic design automation
A 2-dimensional placement algorithm for the layout of electrical circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
A min-cut placement algorithm for general cell assemblies based on a graph representation
25 years of DAC Papers on Twenty-five years of electronic design automation
A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Automatic synthesis of Boolean equations using programmable array logic
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A neural network design for circuit partitioning
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient final placement based on nets-as-points
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An evolution-based approach to partitioning ASIC systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Geometric embeddings for faster and better multi-way netlist partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Multiple-Way Network Partitioning with Different Cost Functions
IEEE Transactions on Computers
A fast and stable hybrid genetic algorithm for the ratio-cut partitioning problem on hypergraphs
DAC '94 Proceedings of the 31st annual Design Automation Conference
A probability-based approach to VLSI circuit partitioning
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
A quadratic metric with a simple solution scheme for initial placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A data structure for circuit net lists
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Hypergraph-Partitioning-Based Decomposition for Parallel Sparse-Matrix Vector Multiplication
IEEE Transactions on Parallel and Distributed Systems
Decomposition of logic networks into silicon
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The VLSI design automation assistant: what's in a knowledge base
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Period-Based Load Partitioning and Assignment for Large Real-Time Applications
IEEE Transactions on Computers
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Micro
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Placement of irregular circuit elements on non-uniform gate arrays
DAC '83 Proceedings of the 20th Design Automation Conference
GRAFOS - A symbolic routing language
DAC '73 Proceedings of the 10th Design Automation Workshop
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
Some experimental results on placement techniques
DAC '76 Proceedings of the 13th Design Automation Conference
Common feature techniques for discrete optimization
DAC '76 Proceedings of the 13th Design Automation Conference
A 2-dimensional placement algorithm for the layout of electrical circuits.
DAC '76 Proceedings of the 13th Design Automation Conference
An iterative algorithm for placement and assignment of integrated circuits
DAC '75 Proceedings of the 12th Design Automation Conference
A logic partitioning procedure by interchanging clusters
DAC '75 Proceedings of the 12th Design Automation Conference
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
The planar package planner for system designers
DAC '82 Proceedings of the 19th Design Automation Conference
A placement algorithm for polycell LSI and ITS evaluation
DAC '82 Proceedings of the 19th Design Automation Conference
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
Advanced LILAC - an Automated Layout Generation system for MOS/LSIs
DAC '74 Proceedings of the 11th Design Automation Workshop
An improved graph-theoretic model for the circuit layout problem
DAC '74 Proceedings of the 11th Design Automation Workshop
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A partitioning technique for LSI chips
ACM SIGDA Newsletter
Good Layouts for Pattern Recognizers
IEEE Transactions on Computers
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
Parallel multilevel algorithms for hypergraph partitioning
Journal of Parallel and Distributed Computing
Multi-level direct K-way hypergraph partitioning with multiple constraints and fixed vertices
Journal of Parallel and Distributed Computing
Optimal block-tridiagonalization of matrices for coherent charge transport
Journal of Computational Physics
Hypergraph Cuts & Unsupervised Representation for Image Segmentation
Fundamenta Informaticae
ACISP'10 Proceedings of the 15th Australasian conference on Information security and privacy
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
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Partitioning algorithms for electrical circuits are often based on the heuristic manipulation of a simple element-to-element interconnection matrix. However, the element-to-element interconnection matrix does not properly represent an electrical interconnection, or “net”, among more than two elements. This paper expands on several aspects of the discrepancy: 1) its source, 2) the circumstances under which it is likely to be significant, and its magnitude for typical circuits, and 3) the comparative difficulty and expense of using a more appropriate representation. A physically correct “net-cut” model is presented. This model is computationally straightforward and is easily adapted to the typical heuristic solution strategies. The “net-cut” model is coupled with the Kernighan-Lin partitioning algorithm [3]; using the same algorithm, comparisons with the “edge-cut” model demonstrate that the correct model reduces net-cuts by 19 to 50% for four digital logic circuits.