A neural network design for circuit partitioning

Authors:
J.-S. Yih;P. Mazumder
Affiliations:
Department of Electrica, Engineering and Computer Science, The University of Michigan, Ann Arbor, MI;Department of Electrica, Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

This paper proposes a neural network model for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of a circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with that achieved by Fiduccia and Mattheyses algorithm.