An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
An iterative algorithm for placement and assignment of integrated circuits
DAC '75 Proceedings of the 12th Design Automation Conference
A simple, efficient design automation processor
DAC '74 Proceedings of the 11th Design Automation Workshop
Constructing test cases for partitioning heuristics
IEEE Transactions on Computers
A min-cut placement algorithm for general cell assemblies based on a graph representation
25 years of DAC Papers on Twenty-five years of electronic design automation
A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
Multiple-Way Network Partitioning
IEEE Transactions on Computers
A neural network design for circuit partitioning
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient final placement based on nets-as-points
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Flexible transistor matrix (FTM)
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multiple-Way Network Partitioning with Different Cost Functions
IEEE Transactions on Computers
Interconnection synthesis with geometric constraints
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
Potential-NRG: placement with incomplete data
DAC '98 Proceedings of the 35th annual Design Automation Conference
A quadratic metric with a simple solution scheme for initial placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning by iterative deletion
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The VLSI design automation assistant: what's in a knowledge base
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
On the relative placement and the transportation problem for standard-cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Consistent floorplanning with super hierarchical constraints
Proceedings of the 2001 international symposium on Physical design
A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
Improved cut sequences for partitioning based placement
Proceedings of the 38th annual Design Automation Conference
A placement technique based on minimization and even distribution of crossovers
ACM SIGDA Newsletter
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Effective partition-driven placement with simultaneous level processing and global net views
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
PIAF: Efficient IC Floor Planning
IEEE Expert: Intelligent Systems and Their Applications
IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Placement of variable size circuits on LSI masterslices
DAC '81 Proceedings of the 18th Design Automation Conference
An approach to gate assignment and module placement for printed wiring boards
DAC '78 Proceedings of the 15th Design Automation Conference
Comet - a fast component placer
DAC '80 Proceedings of the 17th Design Automation Conference
Gate assignment and pack placement: Two approaches compared
DAC '80 Proceedings of the 17th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
SAGA: An Experimental Silicon Assembler
DAC '82 Proceedings of the 19th Design Automation Conference
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
CGALA-a multi technology Gate Array Layout system
DAC '82 Proceedings of the 19th Design Automation Conference
LAMBDA: A quick, low cost layout design system for master-slice LSI s
DAC '82 Proceedings of the 19th Design Automation Conference
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
PARAGON: a new package for gate matrix layout synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
Placement Using a Localization Probability Model (LPM)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Annealing placement by thermodynamic combinatorial optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
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In this paper we present a class of min-cut placement algorithms for solving some assignment problems related to the physical implementation of electrical circuits. We discuss the need for abandoning classical objective functions based upon distance, and introduce new objective functions based upon "signals cut." The number of signals cut by a line c is a lower bound on the number of routing tracks which must cross c in routing the circuit. Three specific objective functions are introduced and the relationship between one of these and a classical distance measure based upon half-perimeter is presented. Two min-cut placement algorithms are presented. They are referred to as Ouadrature and Slice/Bisection. The concepts of a block and cut line are introduced. These two entities are the major constructs in developing any new min-cut placement algorithm. Most of the concepts presented have been implemented, and some experimental results are given.