A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
The placement problem as viewed from the physics of classical mechanics
DAC '75 Proceedings of the 12th Design Automation Conference
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
A rule-based placement system for printed wiring boards
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Knowledge-based placement technique for printed wiring boards
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
On the relative placement and the transportation problem for standard-cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MCM placement using a realistic thermal model
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Gravity: Fast placement for 3-D VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Routing method for VLSI design using irregular cells
DAC '83 Proceedings of the 20th Design Automation Conference
A standard cell initial placement strategy
DAC '84 Proceedings of the 21st Design Automation Conference
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper presents a new algorithm for the initial placement of hierarchical VLSI circuits. The components to be placed are orthogonal macrocells of variable shape and size. This algorithm combines the advantages of force directed placement and min-cut algorithm. It provides an initial placement which avoids overlapping between cells and includes an estimation of routting area. This algorithm is suitable for regular cell arrangements, too.