An automatic rectilinear partitioning procedure for standard cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Benchmarks for cell-based layout systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An analytical algorithm for placement of arbitrarily sized rectangular blocks
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Near-optimal placement using a quadratic objective function
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On the relative placement and the transportation problem for standard-cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The complexity of design automation problems
DAC '80 Proceedings of the 17th Design Automation Conference
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
On finding most optimal rectangular package plans
DAC '82 Proceedings of the 19th Design Automation Conference
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
Automated generation of layout and control for quantum circuits
Proceedings of the 4th international conference on Computing frontiers
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A new algorithm for circuit packing (or detailed placement) in any rectilinear region called Adaptive Cluster Growth (ACG) is described in analogy to the growth of a low-stress crystal in a cavity of any given shape. ACG is an algorithm suitable for packing of circuit modules, either standard cell or macro cell, in a rectilinear region by refining the result of global placement obtained by such techniques as Force-Directed Relaxation (FDR) or Force-and-Cut placement (FOCUP). The overlaps among modules or overlaps between any module and chip boundary are removed, which exist in the global placement result, are removed in ACG in such a way that the estimation of the total routing length is kept as low as possible. Our experiment with standard cell circuits in Benchmark data has shown that ACG outperforms or performs close to other packing techniques, which are applicable only for rectangular region, even in rectangular region case. Examples are shown to demonstrate the packing of standard cell circuits in arbitrary-shaped regions. An efficient tiling scheme for representing the rectilinear-shaped cluster and region boundary is also described.