A fast quantum mechanical algorithm for database search
STOC '96 Proceedings of the twenty-eighth annual ACM symposium on Theory of computing
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region
EURO-DAC '90 Proceedings of the conference on European design automation
Proceedings of the 32nd annual international symposium on Computer Architecture
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Interconnection Networks for Scalable Quantum Computers
Proceedings of the 33rd annual international symposium on Computer Architecture
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
Proceedings of the 33rd annual international symposium on Computer Architecture
System design for large-scale ion trap quantum information processor
Quantum Information & Computation
Running a Quantum Circuit at the Speed of Data
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A fault tolerant, area efficient architecture for Shor's factoring algorithm
Proceedings of the 36th annual international symposium on Computer architecture
A library-based synthesis methodology for reversible logic
Microelectronics Journal
Quantum physical synthesis: Improving physical design by netlist modifications
Microelectronics Journal
Auxiliary qubit selection: a physical synthesis technique for quantum circuits
Quantum Information Processing
Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A quantum physical design flow using ILP and graph drawing
Quantum Information Processing
Quantum circuit physical design methodology with emphasis on physical synthesis
Quantum Information Processing
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We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we investigate grid-based layouts and show a performance variance of four times as we vary grid structure and initial qubit placement. We then propose two polynomial-time design heuristics: a greedy algorithm suitable for small, congestion-free quantum circuits and a dataflow-based analysis approach to placement and routing with implicit initial placement of qubits. Finally, we show that our dataflow-based heuristic generates better layouts than the state-of-the-art automated grid-based layout and scheduling mechanism in terms of latency and potential pipelinability, but at the cost of some area.