A fast quantum mechanical algorithm for database search
STOC '96 Proceedings of the twenty-eighth annual ACM symposium on Theory of computing
Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer
SIAM Journal on Computing
Quantum computation and quantum information
Quantum computation and quantum information
Algorithmic Patterns for Orthogonal Graph Drawing
GD '98 Proceedings of the 6th International Symposium on Graph Drawing
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Automated generation of layout and control for quantum circuits
Proceedings of the 4th international conference on Computing frontiers
Running a Quantum Circuit at the Speed of Data
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A fault tolerant, area efficient architecture for Shor's factoring algorithm
Proceedings of the 36th annual international symposium on Computer architecture
Improving Latency of Quantum Circuits by Gate Exchanging
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Quantum physical synthesis: Improving physical design by netlist modifications
Microelectronics Journal
Auxiliary qubit selection: a physical synthesis technique for quantum circuits
Quantum Information Processing
Surface-electrode architecture for ion-trap quantum information processing
Quantum Information & Computation
On the transport of atomic ions in linear and multidimensional ion trap arrays
Quantum Information & Computation
Quantum Circuit Simplification and Level Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11 % for a set of attempted benchmarks and by about 9 % for another set of benchmarks compared with the best in literature.