A method for generating random circuits and its application to routability measurement
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Proceedings of the 32nd annual international symposium on Computer Architecture
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Gate-level simulation of quantum circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Interconnection Networks for Scalable Quantum Computers
Proceedings of the 33rd annual international symposium on Computer Architecture
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
Proceedings of the 33rd annual international symposium on Computer Architecture
Automated generation of layout and control for quantum circuits
Proceedings of the 4th international conference on Computing frontiers
Microcoded Architectures for Ion-Tap Quantum Computers
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Running a Quantum Circuit at the Speed of Data
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Synthesis of quantum-logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum physical synthesis: Improving physical design by netlist modifications
Microelectronics Journal
Auxiliary qubit selection: a physical synthesis technique for quantum circuits
Quantum Information Processing
Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers
Proceedings of the 40th Annual International Symposium on Computer Architecture
A 2D nearest-neighbor quantum architecture for factoring in polylogarithmic depth
Quantum Information & Computation
A quantum physical design flow using ILP and graph drawing
Quantum Information Processing
Quantum circuit physical design methodology with emphasis on physical synthesis
Quantum Information Processing
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We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder circuits. Our custom CAD flow produces detailed layouts of the physical components and utilizes simulation to analyze circuits in terms of area, latency, and success probability. We introduce a metric, called ADCR, which is the probabilistic equivalent of the classic Area-Delay product. Our error correction optimization can reduce ADCR by order of magnitude or more. Contrary to conventional wisdom, we show that the area of an optimized quantum circuit is not dominated exclusively by error correction. Further, our adder evaluation shows that quantum carry-lookahead adders (QCLA) beat ripple-carry adders in ADCR, despite being larger and more complex. We conclude with what we believe is one of most accurate estimates of the area and latency required for 1024-bit Shor's factorization: 7659 mm2 for the smallest circuit and 6 x 108 seconds for the fastest circuit.