Fault-tolerant quantum computation with constant error
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
Pipelined All-to-All Broadcast in All-Port Meshes and Tori
IEEE Transactions on Computers
Quantum computation and quantum information
Quantum computation and quantum information
Proceedings of the 32nd annual international symposium on Computer Architecture
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Architectural implications of quantum computing technologies
ACM Journal on Emerging Technologies in Computing Systems (JETC)
System design for large-scale ion trap quantum information processor
Quantum Information & Computation
Surface-electrode architecture for ion-trap quantum information processing
Quantum Information & Computation
Automated generation of layout and control for quantum circuits
Proceedings of the 4th international conference on Computing frontiers
Proceedings of the 34th annual international symposium on Computer architecture
High-level interconnect model for the quantum logic array architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Microcoded Architectures for Ion-Tap Quantum Computers
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Running a Quantum Circuit at the Speed of Data
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A fault tolerant, area efficient architecture for Shor's factoring algorithm
Proceedings of the 36th annual international symposium on Computer architecture
Quantum physical synthesis: Improving physical design by netlist modifications
Microelectronics Journal
Auxiliary qubit selection: a physical synthesis technique for quantum circuits
Quantum Information Processing
Teleportation of composite systems for communication and information processing
Quantum Information & Computation
Quantum circuit physical design methodology with emphasis on physical synthesis
Quantum Information Processing
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The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems.