Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric

Authors:
Mohammad Javad Dousti;Massoud Pedram
Affiliations:
University of Southern California, Los Angeles, CA;University of Southern California, Los Angeles, CA
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 3
Cited 1

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An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures

Proceedings of the 32nd annual international symposium on Computer Architecture
Automated generation of layout and control for quantum circuits

Proceedings of the 4th international conference on Computing frontiers

Quantum circuit physical design methodology with emphasis on physical synthesis

Quantum Information Processing

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Abstract

Quantum computers are exponentially faster than their classical counterparts in terms of solving some specific, but important problems. The biggest challenge in realizing a quantum computing system is the environmental noise. One way to decrease the effect of noise (and hence, reduce the overhead of building fault tolerant quantum circuits) is to reduce the latency of the quantum circuit that runs on a quantum circuit. In this paper, a novel algorithm is presented for scheduling, placement, and routing of a quantum algorithm, which is to be realized on a target quantum circuit fabric technology. This algorithm, and the accompanying software tool, advances state-of-the-art in quantum CAD methodologies and methods while considering key characteristics and constraints of the ion-trap quantum circuit fabric. Experimental results show that the presented tool improves results of the previous tool by about 41%.