Short factorizations of permutations into transpositions
Discrete Mathematics
Quantum computation and quantum information
Quantum computation and quantum information
A 1.5GHz third generation itanium® 2 processor
Proceedings of the 40th annual Design Automation Conference
Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation
Proceedings of the 1st conference on Computing frontiers
Quantum logic synthesis by symbolic reachability analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 32nd annual international symposium on Computer Architecture
Data structures and algorithms for simplifying reversible circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automated generation of layout and control for quantum circuits
Proceedings of the 4th international conference on Computing frontiers
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Techniques for the synthesis of reversible Toffoli networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel synthesis algorithm for reversible circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Communications of the ACM - Web science
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Reversible Logic Synthesis with Output Permutation
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
A cycle-based synthesis algorithm for reversible logic
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On figures of merit in reversible and quantum logic designs
Quantum Information Processing
Low Power Design Essentials
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Synthesis of reversible logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of quantum-logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Synthesis of Reversible Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantum Circuit Simplification and Level Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis and optimization of reversible circuits—a survey
ACM Computing Surveys (CSUR)
Depth-optimized reversible circuit synthesis
Quantum Information Processing
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Synthesis of reversible logic has received significant attention in the recent years and many synthesis approaches for reversible circuits have been proposed so far. In this paper, a library-based synthesis methodology for reversible circuits is proposed where a reversible specification is considered as a permutation comprising a set of cycles. To this end, a pre-synthesis optimization step is introduced to construct a reversible specification from an irreversible function. In addition, a cycle-based representation model is presented to be used as an intermediate format in the proposed synthesis methodology. The selected intermediate format serves as a focal point for all potential representation models. In order to synthesize a given function, a library containing seven building blocks is used where each building block is a cycle of length less than 6. To synthesize large cycles, we also propose a decomposition algorithm which produces all possible minimal and inequivalent factorizations for a given cycle of length greater than 5. All decompositions contain the maximum number of disjoint cycles. The generated decompositions are used in conjunction with a novel cycle assignment algorithm which is proposed based on the graph matching problem to select the best possible cycle pairs. Then, each pair is synthesized by using the available components of the library. The decomposition algorithm together with the cycle assignment method are considered as a binding method which selects a building block from the library for each cycle. Finally, a post-synthesis optimization step is introduced to optimize the synthesis results in terms of different costs. To analyze the proposed methodology, various experiments are performed. Our analyses on the available reversible benchmark functions reveal that the proposed library-based synthesis methodology can produce low-cost circuits in some cases compared with the current approaches. The proposed methodology always converges and it typically synthesizes a give function fast. No garbage line is used for even permutations.