Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Transformation rules for designing CNOT-based quantum circuits
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Quantum computation and quantum information
Quantum computation and quantum information
Reversible logic circuit synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A transformation based algorithm for reversible logic synthesis
Proceedings of the 40th annual Design Automation Conference
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BDD minimization by scatter search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Quantum Circuit Simplification Using Templates
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Majority-based reversible logic gates
Theoretical Computer Science
Synthesis of quantum logic circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analysis and synthesis of quantum circuits by using quantum decision diagrams
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reversible logic synthesis with Fredkin and Peres gates
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A novel Toffoli network synthesis algorithm for reversible logic
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Novel Transformation-Based Algorithm for Reversible Logic Synthesis
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
A library-based synthesis methodology for reversible logic
Microelectronics Journal
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Reversible quantum logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability analysis where the primary inputs are purely binary. we use symbolic reachability analysis, a technique most commonly used in model checking (a way of formal verification), to synthesize the optimum quantum circuits. We present an exact synthesis method with optimal quantum cost and a speedup method with non-optimal quantum cost. Both our methods guarantee the synthesizeability of all reversible circuits. Unlike previous works which use permutative reversible gates, we use a lower level library which includes non-permutative quantum gates. For the first time, problems in quantum logic synthesis have been reduced to those of multiple-valued logic synthesis thus reducing the search space and algorithm complexity. We synthesized quantum circuits for gate, half-adder, full-adder, etc. with the smallest cost.. Our approach obtains the minimum cost quantum circuits for Miller's gate, half-adder, and full-adder, which are better than previous results. In addition, we prove the minimum quantum cost (using our elementary quantum gates) for Fredkin, Peres, and Toffoli gates. Our work constitutes the first successful experience of applying satisfiability with formal methods to quantum logic synthesis.