Board-level multiterminal net assignment for the partial cross-bar architecture

Authors:
Xiaoyu Song;William N. N. Hung;Alan Mishchenko;Malgorzata Chrzanowska-Jeske;Andrew Kennings;Alan Coppola
Affiliations:
Department of Electrical and Computer Engineering, Portland State University, Portland, OR;Department of Electrical and Computer Engineering, Portland State University, Portland, OR;Department of Electrical and Computer Engineering, Portland State University, Portland, OR;Department of Electrical and Computer Engineering, Portland State University, Portland, OR;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1 Canada;Cypress Semiconductor, Beaverton, OR
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Year:
2003

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Abstract

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.