Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A Template for Scatter Search and Path Relinking
AE '97 Selected Papers from the Third European Conference on Artificial Evolution
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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We address the problem of board-level multiterminal net assignment in FPGA-based logic emulation. We present a novel mathematical model for this problem. A powerful metaheuristic approach, called scatter search, is adopted. Effective heuristics are incorporated for accelerating the optimization search process. Experimental results demonstrate the promising performance of our approach.