A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Architecture driven circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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In this paper, we study the net assignment problem for a logic emulation system in the folded-Clos network interconnection, also referred to as the “partial crossbar interconnection structure”. Net assignment of two-terminal nets in this interconnection structure is guaranteed to be completed in polynomial time. However, net assignment of multiterminal nets becomes NP-complete. A previous paper by Butts et al. (1992) has proposed a simple heuristic to perform net assignment for multiterminal nets. Its results showed that it failed to complete routing of all nets for many cases. It is inadequate to have a net assignment algorithm which does not guarantee an exact solution, as the failure of interconnecting field programmable gate arrays (FPGA's) will result in the failure of mapping to the computing engine as a whole and will result in redoing the previous steps, e.g., partitioning of circuits. Therefore, we propose an exact algorithm to solve the net assignment problem. The exact algorithm will find a solution if one exists. However, the exact algorithm may take exponential time. Accordingly, a two-phase approach is taken in this paper. A time-efficient heuristic method is used first. The exact solver will be called only if the heuristic fails to deliver a solution