Board-level multiterminal net assignment

Authors:
Xiaoyu Song;William N. N. Hung;Alan Mishchenko;Malgorzata Chrzanowska-Jeske;Alan Coppola;Andrew Kennings
Affiliations:
Portland State University, Portland, OR;Intel Corporation, Hillsboro, OR;Portland State University, Portland, OR;Portland State University, Portland, OR;Cypress Semiconductor, Beaverton, OR;University of Waterloo, Waterloo, Ontario, Canada
Venue:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Year:
2002

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Abstract

The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach transforms the FPGA board-level routing task into a single, large Boolean equation with the property that any assignment of input variables that satis驴fies the equation specifies a valid routing. The approach considers all nets simultaneously and the absence of a satisfying assignment implies that the layout is unroutable. We use two of the fastest SAT solvers: Chaff and DLM to perform our experiments. Empirical re驴sults show that the method is time-efficient and applicable to large layout problem instances.