Linear programming and network flows (2nd ed.)
Linear programming and network flows (2nd ed.)
Field-programmable gate arrays
Field-programmable gate arrays
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
On optimal board-level routing for FPGA-based logic emulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
Circuit clustering for delay minimization under area and pin constraints
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System [3] and the Enterprise Emulation System [5] manufactured by Quickturn Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets [10,11]. In this paper, we show how multi-terminal nets can be handled by decomposition into two-terminal nets. We show that the multi-terminal net decomposition problem can be modelled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there is a feasible decomposition and gives one whenever such a decomposition exists.