A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
Performance-driven system partitioning on multi-chip modules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral synthesis: digital system design using the synopsys behavioral compiler
Behavioral synthesis: digital system design using the synopsys behavioral compiler
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Board-level multiterminal net routing for FPGA-based logic emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Transmogrifier-2: a 1 million gate rapid prototyping system
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
AnyBoard: An FPGA-Based, Reconfigurable System
IEEE Design & Test
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Mesh Routing Topologies for Multi-FPGA Systems
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
MORRPH: a modular and reprogrammable real-time processing hardware
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On optimal board-level routing for FPGA-based logic emulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Incremental reconfiguration of multi-FPGA systems
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Implementation of BEE: a real-time large-scale hardware emulation engine
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Testing Layered Interconnection Networks
IEEE Transactions on Computers
Designing BEE: a hardware emulation engine for signal processing in low-power wireless applications
EURASIP Journal on Applied Signal Processing
MLMIN: A multicore processor and parallel computer network topology for multicast
Computers and Operations Research
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Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture; the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Arno92] [Butt92] [Hauc94] [Apti96] [Vuil96] and previous research has shown that the partial crossbar is one of the best existing architectures [Kim96] [Khal97]. In this paper we propose a new routing architecture, called the Hybrid Complete-Graph and Partial-Crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hard-wired and programmable connections between the FPGAs.We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and inter-chip routing tools were developed, with particular attention paid to architecture-appropriate inter-chip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20% more than the new HCGP architecture and as much as 35% more. Furthermore, the critical path delay for designs implemented on the partial crossbar increased, and were on average 9% more than the HCGP architecture and up to 26% more.Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture: the proportion of hard-wired connections versus programmable connections, to determine its best value.