MLMIN: A multicore processor and parallel computer network topology for multicast

Authors:
Dietmar Tutsch;Günter Hommel
Affiliations:
Technische Universität Berlin, Institute of Computer Engineering and Microelectronics, 10587 Berlin, Germany;Technische Universität Berlin, Institute of Computer Engineering and Microelectronics, 10587 Berlin, Germany
Venue:
Computers and Operations Research
Year:
2008

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Abstract

In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than today's shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast traffic particularly benefit from the new topology.