SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Implementation issues of image texture analysis and segmentation
Microprocessing and Microprogramming - Special volume: short notes from Euromicro '92
A gate-level reconfigurable Monte Carlo processor
Journal of VLSI Signal Processing Systems - Special issue on field-programmable gate arrays
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
A FIELD-PROGRAMMABLE PROTOTYPING BOARD: XC4000 BORG USER''S GUIDE
A FIELD-PROGRAMMABLE PROTOTYPING BOARD: XC4000 BORG USER''S GUIDE
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
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Abstract: MORRPH is a general-purpose reconfigurable processing unit, primarily intended for real-time 2-dimensional image processing. Its flexible architecture allows it to be used for other applications including 1-dimensional signal processing, 2-dimensional cellular automata problems, and 3-dimensional image processing. The modular, open-ended (incompletely specified) architecture consists of a rectangular mesh of processing elements. Each processing element contains one socket for a field programmable gate array (FPGA) chip and one socket for support processing chips. The FPGA chips provide an array of logic resources, consisting of combinational logic functions, flip-flops, and interconnections. Empty support sockets allow several discrete IC chips to be tightly coupled to each FPGA, the type of IC is determined by the individual requirements of the task to be performed by the MORRPH board. This allows the support chips to implement functions that are not efficiently realized by the FPGAs. These memory, arithmetic, or processing support chips are specified when a particular application is compiled for the MORRPH board. If a single MORRPH board does not provide enough computational power for a particular application, several MORRPH boards can be interconnected to solve the task. The MORRPH architecture is implemented as an adapter The modular nature of the MORRPH architecture at both the chip and board level allows a very efficient implementation of a required machine vision task.