An FPGA-based hardware accelerator for image processing
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Flexible image acquisition using reconfigurable hardware
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
MORRPH: a modular and reprogrammable real-time processing hardware
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A design flow for protecting FPGA-based systems against single event upsets
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Routability and Fault Tolerance of FPGA Interconnect Architectures
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Single-event-upset (SEU) awareness in FPGA routing
Proceedings of the 44th annual Design Automation Conference
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
On-line control flow error detection using relationship signatures among basic blocks
Computers and Electrical Engineering
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Evaluation and analysis of an on-line error detection monitoring technique
Computers and Electrical Engineering
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This paper presents three methods to reduce the system failures resulted from soft errors: (1) an adaptive redundancy-based method that utilizes unused resources to tolerate the effects of soft errors in SRAM-based FPGAs; (2) an SEU-aware method in CAD flow of SRAM-based FPGAs to mitigate the effects of soft errors which is based on T-VPack and VPR tools and functions without any redundancy; and finally, (3) combination of these two methods to realize whether these SEU reduction methods are cumulative or not when they are applied in sequence. The effects of these methods have been investigated on several MCNC benchmarks. The results show that the system failure rate of circuits implemented on FPGAs decreases about 3.59% using the first method, 4.60%, 10.09%, and 12.45% in three cases of the second method, and 7.47%, 15.94%, and 17.43% in three cases of the third method. These results show that the effect of combining the first and the second methods is cumulative.