Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Multiple Errors Produced by Single Upsets in FPGA Configuration Memory: A Possible Solution
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Soft Error Mitigation for SRAM-Based FPGAs
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
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This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated based on several MCNC benchmarks using VPR tool. The experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs about 20% on average compared to the traditional ones.