Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs

Authors:
E. Syam Sundar Reddy;Vikram Chandrasekhar;M. Sashikanth;V. Kamakoti;N. Vijaykrishnan
Affiliations:
Indian Institute of Technology at Madras;Indian Institute of Technology at Madras;Indian Institute of Technology at Madras;Indian Institute of Technology at Madras;Pennsylvania State University
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

Citing 0
Cited 5

Single-event-upset (SEU) awareness in FPGA routing

Proceedings of the 44th annual Design Automation Conference
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes

Microelectronics Journal
Mitigating FPGA interconnect soft errors by in-place LUT inversion

Proceedings of the International Conference on Computer-Aided Design
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.