VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Testing for Resistive Shorts in FPGA Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
Single-event-upset (SEU) awareness in FPGA routing
Proceedings of the 44th annual Design Automation Conference
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 47th Design Automation Conference
RALF: reliability analysis for logic faults: an exact algorithm and its applications
Proceedings of the Conference on Design, Automation and Test in Europe
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Mitigating FPGA interconnect soft errors by in-place LUT inversion
Proceedings of the International Conference on Computer-Aided Design
In-place decomposition for robustness in FPGA
Proceedings of the International Conference on Computer-Aided Design
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Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.