Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Decomposable negation normal form
Journal of the ACM (JACM)
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A compiler for deterministic, decomposable negation normal form
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Reliability analysis for a logic circuit is one of the primary tasks in fault-tolerant logic synthesis. Given a fault model, it quantifies the impact of faults on the full-chip fault rate. We present RALF, an exact algorithm for calculating the reliability of a logic circuit. RALF is based on the compilation of a circuit to deterministic decomposable negation normal form (d-DNNF), a representation for Boolean formulas that can be more succinct than BDDs. Our algorithm can solve a large set of MCNC benchmark circuits within 5 minutes, enabling an optimality study of Monte Carlo simulation, a popular estimation method for reliability analysis, on real benchmark circuits. Our study shows that Monte Carlo simulation with a small set of random vectors generally has a high fidelity for the computation of full-chip fault rates and the criticality of single gates. While we focus on reliability analysis, RALF can also be used to efficiently locate random pattern resistant faults. This can be used to identify where methods other than random simulation should be used for accurate criticality calculations and where to enhance the testability of a circuit.