A strategy for reliability assessment of future nano-circuits
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
RALF: reliability analysis for logic faults: an exact algorithm and its applications
Proceedings of the Conference on Design, Automation and Test in Europe
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic error modeling for nano-domain logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate and effective algorithm for estimating the reliability of digital combinational circuits
Proceedings of the 46th Annual Simulation Symposium
| Hi-index | 0.02 |
We propose a novel single event fault/error model based on Logic Induced Fault Encoded Directed Acyclic Graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in nano-domain logic block) that depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, we show that we are able to estimate detection probabilities of single-event faults/errors onISCASý85 benchmarks with high accuracy (zero-error), linear space requirement complexity, and with an order of magnitude (驴 5 times) reduction in estimation time over corresponding BDD based approaches.