Probabilistic reasoning in intelligent systems: networks of plausible inference
Probabilistic reasoning in intelligent systems: networks of plausible inference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Probabilistic Networks and Expert Systems
Probabilistic Networks and Expert Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Effect of Threshold Voltages on the Soft Error Rate
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
An Accurate Probalistic Model for Error Detection
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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With device size shrinking and fast rising frequency ranges, the effect of cosmic radiations and alpha particles known as single-event upset (SEU) and single-event transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of SEU sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure, and gate delays on SEU sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but it also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate nonsimulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.