Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An ILP Formulation for Reliability-Oriented High-Level Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Energy-aware computation duplication for improving reliability in embedded chip multiprocessors
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compiler-directed selective data protection against soft errors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Improving scratch-pad memory reliability through compiler-guided data block duplication
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Systematic Approach to Automatically Generate Multiple Semantically Equivalent Program Versions
Ada-Europe '08 Proceedings of the 13th Ada-Europe international conference on Reliable Software Technologies
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical model for soft error critical charge of nanometric SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Due to technology scaling, smaller devices and lower operating voltages, next generation circuits are highly susceptible to soft errors. Another important problem confronting silicon scaling is static power consumption. In this paper, we analyze the effect of increasing threshold voltage (widely used for reducing static power consumption) on the soft error rate (SER). We .nd that increasing threshold voltage improves SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses. We also show that clever use of high Vt can improve the robustness of 6T-SRAMs.