Case study of reliability-aware and low-power design

Authors:
Shengqi Yang;Wenping Wang;Tiehan Lu;Wayne Wolf;N. Vijaykrishnan;Yuan Xie
Affiliations:
Digital Home Group, Intel Corporation, Chandler, AZ and Electrical Engineering Department, Princeton University, Princeton, NJ;Electrical Engineering Department, Arizona State University, Tempe, AZ;Digital Home Group, Intel Corporation, Chandler, AZ and Electrical Engineering Department, Princeton University, Princeton, NJ;Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA and Electrical Engineering Department, Princeton University, Princeton, NJ;Computer Science and Engineering Department, Pennsylvania State University, University Park, PA;Computer Science and Engineering Department, Pennsylvania State University, University Park, PA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 31
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Abstract

Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.